Simple Computation of DIT FFT
نویسنده
چکیده
FFT and IFFT algorithm plays an important role in design of digital signal processing. This paper describes the design of Decimation in Time-Fast Fourier Transform (DIT-FFT). The proposed design is a novel 16 bit word length processor, which is implemented with radix-2, based 8 point FFT. This approach reduces the multiplicative complexity which exists in conventional FFT implementation. For the number representation of FFT fixed point arithmetic has been used. The design is implemented using Verilog HDL language. KeywordsDIT-FFT, Complex multiplication, Verilog, FPGA, Radix-2.
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